library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity PCMUX_logic is
    port(Clk: in bit; PCMUX: in  bit_vector(1  downto 0);
         PCval,BUS_in,ADDR_out: in unsigned(15 downto 0);
         PCMUX_out: out unsigned(15 downto 0));
    end entity PCMUX_logic;
    
architecture build of PCMUX_logic is
    
    begin
    
        process(PCMUX,PCval,BUS_in,ADDR_out)
            begin
                --if Clk = '1' and Clk'event then
                if PCMUX = "00" then
                    PCMUX_out <= PCval + 2;
                elsif PCMUX = "01" then
                    PCMUX_out <= BUS_in;
                elsif PCMUX = "10" then
                    PCMUX_out <= ADDR_out;
                else PCMUX_out <= "0000000000000000";
                end if;
            --end if;
            end process;
    end build;